1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor apparatus and, specifically, to a method of manufacturing a semiconductor apparatus having a vertical MOSFET (metal oxide semiconductor field effect transistor).
2. Description of Related Art
A vertical MOSFET (metal oxide semiconductor field effect transistor) is normally used as a power MOSFET for switching power to supply high voltage or large current. In the vertical MOSFET, a source electrode is formed on one surface of a semiconductor substrate, and a drain electrode is formed on the other surface of the semiconductor substrate. Therefore, the current flows in the vertical direction of the semiconductor substrate. It is required that the power MOSFET has as small ON-resistance as possible to save power consumption.
Specifically, ON-resistance per area can be reduced by narrowing the distance between two adjacent gate electrode portions and increasing the number of channel regions per area. In a conventional vertical MOSFET as disclosed in U.S. Pat. No. 4,767,722, a body contact region passing through the source region is formed between two adjacent gate electrode portions. The two adjacent gate electrode portions mean two certain opposed portions of a gate electrode that are arranged in parallel each other. A plurality of gate electrode portions are connected to each other and form one lattice-shaped gate electrode as shown in FIG. 9 of U.S. Pat. No. 4,767,722. Thus, one source region, a body contact region, and the other source region are formed in order between two adjacent gate electrode portions. In order to narrow the distance between the two gate electrode portions, a contact hole for connecting the source electrode and the body region is formed between the two gate electrode portions as disclosed in International Patent Publication No. WO03/046999. However, there is a limit to narrow the distance between the two adjacent gate electrode portions.
On the other hand, a vertical MOSFET in which the distance between the two gate electrode portions is ultimately narrowed with no body contact region or no contact hole passing through the source region that is arranged between the two gate electrode portions is disclosed in Japanese Unexamined Patent Publications No. 2003-101027, No. 2000-252468, and No. 2005-191359 for example. FIG. 5 is a sectional view showing a semiconductor apparatus 1 which is a prototype similar to a conventional vertical P-channel MOSFET disclosed in Japanese Unexamined Patent Publication No. 2003-101027. FIG. 6 is a sectional view showing a semiconductor apparatus 1 which is a vertical N-channel MOSFET manufactured in the same way as the P-channel MOSFET in FIG. 5. The each semiconductor apparatus 1 has a drain region 2, a body region 3, a source region 4, a trench 5, a gate insulation film 6, a gate electrode portion 7, interlayer insulation film 8, a drain electrode 9, and a source electrode 10. As mentioned above, owing to no body contact region or no contact hole passing through the source region 4 between the two gate electrode portions 7, the distance between the two gate electrode portions 7 can be narrowed. Now, the drain region 2 of a vertical P-channel MOSFET generally has a two-layer structure of a P+-type substrate and a P−-type epitaxial layer. Also the drain region 2 of a vertical N-channel MOSFET generally has a two-layer structure of an N+-type substrate and an N−-type epitaxial layer. In FIGS. 5 and, however, the drain region 2 is simplified to one layer structure symbolized with “P” and “N” respectively.
ON-resistance can also be reduced by shortening a channel length. Specifically, a shallow body region, a so-called shallow junction, is effective. However, it is required not to decrease drain-source breakdown voltage.
In the manufacturing process of the vertical P-channel MOSFET illustrated in FIG. 5, the trench 5 is formed after forming the body region 3 and the source region 4. Then, each gate insulation film 6 is formed. Therefore, the shape of the body region 3 and the source region 4 changes near the interface between the gate insulation film 6 formed on the side wall of the trench 5 and the silicon substrate. Specifically, as illustrated in FIG. 5, the concentration of impurities such as boron in the P-type source region 4 decreases near the gate insulation film 6, which leads to the shallow P-type source region 4, since boron diffuses into the gate insulation film 6 during oxidation process. To the contrary, the concentration of impurities such as phosphorus and arsenic in the N-type body region 3 increases near the gate insulation film 6, which leads to the deep N-type body region 3, since impurities segregate near the gate insulation film 6. Therefore, the channel length becomes long and which leads to high ON-resistance. Furthermore, a large process margin is required since the channel length fluctuates so widely that it is difficult to control.
On the other hand, in the N-channel MOSFET shown in FIG. 6 which is manufactured in the same way as the P-channel MOSFET in FIG. 5, the channel length becomes short and which may unfavorably cause the breakdown voltage to decrease and the leak current to increase.
In the vertical MOSFET disclosed in Japanese Unexamined Patent Publication No. 2000-252468, the trench 5 is formed after forming the body region 3 only. Then, the gate insulation film 6 is formed. Also, in this case, even though the channel length is longer than the N-channel MOSFET of FIG. 6, it becomes short, which may unfavorably cause the breakdown voltage to decrease and the leak current to increase.
As mentioned above, in the vertical MOSFETs of the related art, the channel length fluctuates so widely that it is difficult to control. Therefore, it is difficult to reduce ON-resistance by a shallow junction in practice.